1. Field of the Invention
The present invention relates to a memory control device interposed between a pair of function circuits, such as image processing circuits in a digital copying machine, for controlling a memory, such as a line memory storing a single line of data.
2. Description of the Prior Art
There has been commonly used a digital copying machine where an image scanner, for example, optically reads an image on an original sheet to obtain image data, and then, after the image data is processed in various ways, such as outline emphasizing, black and white inverting, and the like, an image is reproduced on a copying sheet. Image formation in such a copying machine, for example, is accomplished by scanning a surface of a photoconductor with laser light modulated in accordance with the image data to form an electrostatic latent image, developing the electrostatic latent image into a toner image, and translating and fixing the toner image on a copying sheet.
Original image data corresponding to an output signal from the image scanner is generally processed in any of several ways, such as outline emphasizing, black and white inverting, shading and the like. In order to perform such various ways of image processing, an image processor may include a page memory which can store a page of image data and implement a series of operations to process the image data stored in the page memory. However, it is undesirable to use a large capacity page memory, because this causes an increase in manufacturing cost for the device. Hence, usually such a page memory is not used, and instead a pipeline organization is employed in which image data that has been processed in an image processing circuit is directly transferred to another image processing circuit for the next step of image processing, and in this way, the image data is processed by stages.
With such a pipeline organization, a line memory, which has a single line of storage capacity corresponding to a single scanning line along which an image scanner scans an original sheet, is interposed between the image processing circuits. The reason for this is that in image processing in a digital copying machine, for example, a horizontal synchronizing signal, which provides timing for the start of processing each single line of data, acts as a reference signal. The image processing circuits are reset in accordance with the horizontal synchronizing signal, and thereafter, processing of a single line of image data is started. If any image processing circuit is reset by the horizontal synchronizing signal in the course of processing a single line of image data, the processing of the single line of image data is interrupted, and the desired image processing may not be completed. Hence, it is necessary for the image processing circuit to take data at a specified timing related to the horizontal synchronizing signal to complete the processing of the single line of image data before it is reset in accordance with the horizontal synchronizing signal. It is also necessary to save a single line of image data for a period when the image processing circuit is reset in accordance with the horizontal synchronizing signal. Thus, it is required to provide a line memory which can save a single line of data at the previous and subsequent stages of each image processing circuit.
On the other hand, complicated image processing such as moving an image can be implemented by combining various functions all of which can be completed within a period corresponding to a single cycle of the horizontal synchronizing signal. In this case, the image processing circuits for implementing various functions are generally designed individually. Thus, it is preferable that each image processing circuit be separated from other image processing circuits at its previous and subsequent stages. In view of this, it is necessary to provide a line memory between each pair of the image processing circuits.
FIG. 6 illustrates an exemplary structure where a line memory is interposed between each pair of adjacent image processing circuits. Line memories 3 and 4 are installed before and after image processing circuits 1 and 2. For the line memories 3 and 4, a first-in first-out memory (referred to as "FIFO memory" hereinafter) is generally used. The reason for this is that both the device structure and processing procedure can be simplified since there is no need to generate addresses for FIFO memories and writing and reading data can be simultaneously performed in and from a single memory.
The line memories 3 and 4 write and read image data based upon a system clock SCLK to control transfer of the image data. The line memories 3 and 4 commonly receive a reading authorizing signal MRE having a fixed timing related to the above-mentioned horizontal synchronizing signal, and the image data is read from the line memories 3 and 4 with common timing. The image processing circuits 1 and 2 also commonly receive the reading authorizing signal MRE and produce a writing authorizing signal MWE of which timing is determined based upon the reading authorizing signal MRE and the time required for an inside processing.
When the image processing circuit 1 is designed to conduct an inversion operation for inverting black and white, for example, the image processing circuit 1 is constructed as illustrated in FIG. 7. As can be seen, 8 bit data delivered by a line 6 is temporarily latched by a latch circuit 7A, based upon a system clock SCLK, and then is inverted by an inverting circuit 8, and thereafter, is latched by a latch circuit 7B and then output to a line 9. It takes two clocks to complete this inverting procedure through the latch circuits 7A and 7B. Hence, the image processing circuit 1 includes latch circuits 10A and 10B for delaying the reading authorizing signal MRE by two clocks, and a signal passing through the latch circuits 10A and 10B is applied to a line memory 4 at the next stage to act as the writing authorizing signal MWE. Thus, two clocks after the reading authorizing signal MRE is produced and the first data is input to the image processing circuit 1 from the line 6, the writing authorizing signal MWE is produced, and the first data processed on the basis of black and white inversion is delivered by the line 9 to write it in the line memory 4 at the next stage.
FIG. 8 is a timing chart illustrating operation of the structure shown in FIG. 6. The horizontal synchronizing signal HSYNC is a negative logic signal (marked with overline in FIG. 8), and in response to its falling, the image processing circuits 1 and 2 are reset. A fixed time .DELTA.T1 after the rising of the horizontal synchronizing signal HSYNC, the reading authorizing signal MRE rises. For a period the reading authorizing signal MRE is at High level, data stored in the line memories 3 and 4 are sequentially read based upon the system clock SCLK.
The image processing circuit 1 permits the writing authorizing signal MWE to rise at time t42 two system clocks SCLK after time t41 at which the reading authorizing signal MRE rises. This results in image data processed for the two-clock period being written in the line memory 4 at the next stage in a period subsequent to time t42.
The reading authorizing signal MRE maintains a status of High level over a period AT2 required for reading a single line of data. When the reading authorizing signal MRE falls at time t43, the writing authorizing signal MWE falls at time t44 two clocks later the falling. Thus, a single line of data is processed on the basis of the black and white inversion which requires two clocks, and the data processed in this way is stored in the line memory 4.
Although the number of clocks spent for the processing varies from one image processing circuit to another, it is necessary to complete a sequence of processing steps from reading data from the line memory at the previous stage to writing data in the line memory at the next stage in a period .DELTA.TH before the horizontal signal HSYNC again falls, because all of the image processing circuits are reset when the horizontal synchronizing signal HSYNC falls, as stated above. On or before the time the horizontal synchronizing signal HSYNC falls, the image data must be saved in the line memory.
Thus, the number of clocks used in the processing steps in the image processing circuits must be determined so that falling of the writing authorizing signal MWE, which is caused the same number of clocks after falling of the reading authorizing signal MRE, is caused before to falling of the horizontal synchronizing signal HSYNC. In other words, the maximum period of time which can be required for the image processing circuits to complete the required processing is a period corresponding to a period AT3 from the falling of the reading authorizing signal MRE to the falling of the horizontal synchronizing signal HSYNC.
In the case of a digital copying machine capable of copying an original sheet of Japan Industrial Standard Line A, Number 0 (referred to as "A0 size" hereinafter) at its maximum, for line memories 3 and 4, a memory must be used which can store image data consisting of dots corresponding in number to a length of a longer side (corresponding to the length of the shorter side of an A0 size sheet) of a sheet of Japan Industrial Standard Line A, Number 1 (referred to as "A1 size" hereinafter). To constitute such a line memory having a large capacity, a single FIFO memory having a storage capacity corresponding to the number of dots contained in the A1 size sheet may be used, and otherwise a special FIFO memory which can allow a signal for memory extension to be output may be used, arranged in cascade connection. However, such large capacity FIFO memory and special FIFO memory are expensive, and therefore, there lies the disadvantage that the intended apparatus costs more.
Accordingly, there has been proposed a low-priced large-capacity line memory in which a plurality of ordinary FIFO memories which cannot output a signal for memory extension are used, and a memory control device regulates the timing of operations of the plurality of FIFO memories.
FIG. 9 is a block diagram showing a basic structure of the memory control device in the case where a line memory is comprised of three FIFO memories. In FIG. 9, an overline is added to symbols designating signals and the like to show that those signals are in a status of negative logic, but such drawing overline is omitted in this description. A digital copying machine capable of copying an A0 size original sheet would require a storage capacity of about 15,000 dots so as to cover the number of dots of a longer side of an A1 size sheet. Therefore, each of the three FIFO memories has a storage capacity of about 5,000 dots. For example, in reading an image at a density of 400 dots per inch (25.4 mm), the required storage capacity for reading 840 mm length of the shorter side of an A0 size sheet is as follows: EQU 840.times.400.div.25.4=13,228 (dots)
In this case, for example, an image scanner having 14,848 dots for reading may be used. Thus, it is calculated that the line memory must have a storage capacity of about 15,000 dots.
Corresponding to each line memory interposed between each pair of the image processing circuits, memory control circuits 5-1, 5-2, . . . , 5-k (referred to as "memory control circuit 5" en bloc; k is an integer 1 smaller than the number of the image processing circuits) are provided. Each of the memory control circuits 5 includes a counter 11 capable of counting the system clock SCLK and counting 15,000 or more. Also, each of the memory control circuits 5 includes three comparators 12A, 12B and 12C for comparing reference values "4,998", "9,998" and "14,998" with the count value of the counter 11, respectively, to produce a signal at High level upon coincidence.
Signals output from the comparators 12A, 12B, 12C are applied through OR gates 13A, 13B, 13C to input terminals of flip flops 14A, 14B, 14C, respectively. The signals output from the OR gates 13A, 13B, 13C are latched by the flip flops 14A, 14B, 14C, respectively, synchronizing with the rising of the system clock SCLK. Q bar output signals (inverted output signals) of the flip flops 14A, 14B, 14C are applied through AND gates 15A, 15B, 15C to data input terminals of the flip flops 16A, 16B, 16C, respectively. The signals output from the AND gates 15A, 15B, 15C are latched by the flip flops 16A, 16B, 16C, respectively, synchronizing with the rising of the system clock SCLK. Q output signals (noninverted output signals) from the flip flops 16A, 16B, 16C are to act as writing authorizing signals RST1, RST2, RST3 for three FIFO memories, respectively. Those FIFO memories corresponding to the writing authorizing signals RST1, RST2, RST3, are named below "first FIFO memory", "second FIFO memory" and "third FIFO memory", respectively (not shown).
Output signals from the flip flops 14A, 14B, 14C are fed back to the OR gates 13A, 13B, 13C, respectively. This is why once a signal at High level is input to the flip flops 14A, 14B, 14C, the Q bar output signals from those flip flops maintain Low level independent of signals input thereto.
On the other hand, the writing authorizing signal MWE is applied from the image processing circuit at the previous stage to the AND gate 15A, the Q output signal from the flip flop 14A is applied to the AND gate 15B, and the Q output signal from the flip flop 14B is applied to the AND gate 15C. The writing authorizing signal MWE is applied to clear input terminals of the counter 11 and the flip flops 14A, 14B, 14C, 16A, 16B and 16C. They are all maintain clear status for a period when the writing authorizing signal MWE is Low.
FIG. 10 is a timing chart illustrating operation of the memory control circuit. When the writing authorizing signal MWE rises at time t1, the output of the AND gate 15A turns to High while the clear status of the flip flops 14A, 14B, 14C, 16A, 16B and 16C is canceled. When the system clock SCLK rises at time t2, output from the AND gate 15A is latched by the flip flop 16A, and consequently, the writing authorizing signal RST1, corresponding to the first FIFO memory turns to High. This allows the first FIFO memory to receive image data in series from the image processing circuit at the previous stage, synchronizing with the system clock SCLK.
At time t1 the clear status of the counter 11 is also canceled, the system clock SCLK is counted for a period from time t2. When a counting value by the counter 11 coincide with the reference value "4,998" in the comparator 12A, the output from the comparator 12A is inverted from Low to High. Then, once output delivered from the comparator 12A through the OR gate 13A is latched by the flip flop 14A in accordance with the following 4999th system clock SCLK, the Q output from the flip flop 14A becomes High while its Q bar output becomes Low. In this state, the output from the AND gate 15A turns to Low, while the output from the AND gate 15B turns to High. Thus, in accordance with the following 5,000th system clocks SCLK, the Q output from the flip flop 16A is inverted to Low, while the Q output from the flip flop 16B is inverted to High.
In this way, at time t3, 5,000 times input of the system clock SCLK after time t1, the writing authorizing signal RST1 corresponding to the first FIFO memory is inverted to Low, and the writing authorizing signal RST2 corresponding to the second FIFO memory is inverted to High. As a result, instead of the writing in the first FIFO memory, writing in the second FIFO memory is started.
With a similar procedure, at time t4 10,000 times input of the system clock SCLK on and after time t1, the writing authorizing signal RST2 corresponding to the second FIFO memory is inverted to Low, and the writing authorizing signal RST3 corresponding to the third FIFO memory is inverted to High. Thus, writing image data in the third FIFO memory is started. At time t5 15,000 times input of the system clock SCLK after time t1 (or when the writing authorizing signal MWE falls), the writing authorizing signal RST3 is inverted to Low, and thus, writing a single line of image data is completed.
After that, at time t6 a period corresponding to one cycle for processing a single line of image data (e.g., 15,240 clocks) after time t1, the writing authorizing signal MWE rises again, and the operation described above is again performed.
Reading image data from the line memory can be effected with a structure similar to the above, and in this case, the reading authorizing signal MRE may be substituted for the writing authorizing signal MWE.
In the above-mentioned structure, each line memory interposed between each pair of the image processing circuits needs a memory control circuit 5 for controlling writing of image data. Specifically, in the structure shown in FIG. 6, for example, a couple of the memory control circuits 5 are needed to control writing image data in the line memories 3 and 4, and additionally, a further memory control circuit is needed to commonly control reading image data from the line memories 3 and 4. Each line memory needs the memory control circuit 5 to write image data in each line memory because a rising timing of the writing authorizing signal MWE input to each line memory from the image processing circuit at the previous stage varies from one image processing circuit to another. In other words, it is necessary to control FIFO memories constituting each line memory with different timings. With many memory control circuits 5 being used as in the above, however, the device structure is complicated and causes an increase in manufacturing cost.
Moreover, each memory control circuit 5 must have a counter 11 which can count a large value corresponding to the A0 size. A circuit structure of the counter 11 is complicated and the cost is high, thereby making the device structure complicated and the intended device cost more.